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This is a call for participation in the "System Test Access Management" Study Group (also referred to as 'SJTAG'). Those interested in joining the study group or being kept informed of its activities should notify their interest by email to This email address is being protected from spambots. You need JavaScript enabled to view it. or via the group's Contact Page (http://www.sjtag.org/members/contact-us).

The goal of this study group is to explore the feasibility and to develop a project authorization request (PAR), including the scope and purpose, for an IEEE standard that defines methods to allow, in conjunction with existing methods, for the coordination and control of device, board, and sub-system test interfaces to extend access to the system level, by leveraging existing test interface standards (by defining a description to better manage how they are used in the system).

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An SJTAG Green Paper

By Bradford G. Van Treuren, SJTAG Chair Emeritus

(Full size images may be viewed from the gallery at the foot of this article. A description of SJTAG Green Papers can be found here.)

Abstract

In this installment, I will be discussing the contrast between the need to support pre-generated tests, which are able to be replicated for factory testing, versus the need to support interactive configuration and control of an entity during Design Verification Test (DVT), Hardware Debugging (HWDB), and Software Debugging (SWDB).  Both aspects are required to support the introduction of new designs.  SJTAG needs to be able to support both these domains.  The first usage domain deals with the traditional boundary-scan testing.  A model of a circuit is created that defines the topology of the scan chain.  An algorithm is applied to the model and a set of test vectors are created that can be applied to circuits matching that topology without needing to regenerate the vectors.  The other domain concerns only a portion of the whole topology: a Test Data Register (TDR).  This application modifies the configuration of one or more data registers (e.g., TDR) over a period of time to change the behavior of the device the registers reside in.  The flow of the execution may not be the same for each execution of the application.  This is because it is dependent on the state of the device, board, system, or a combination of some set of effectors monitored during the test operation.

Details

An SJTAG Green Paper

By Bradford G. Van Treuren, SJTAG Chair Emeritus

(Full size images may be viewed from the gallery at the foot of this article. A description of SJTAG Green Papers can be found here.)

Abstract

In this paper, I plan to present a comparison and contrast to the issues of chain selection as used by several well known use cases for board level testing.  During the formation of the IEEE 1687 standard draft, there was much debate regarding whether the test engineer should be responsible for configuring the topology of the scan chain inside of a device or should the tooling be able to automatically configure the topology based on what actions were being applied to the hardware.  On one side, engineers like to be able to have control over tools to give them a way to override assumptions a tool uses for cases where they do not match the desired behavior.  Further, engineers have to deal with board and chip designs that do not always comply with a given standard. On the flip side, topologies are getting quite complex and it is difficult and time consuming for an engineer to map out and configure the appropriate topology for a given set of actions.  This is especially true for actions requiring the selection of different instruments residing down separate hierarchical trees inside of a device.  Power management inside devices today complicates this problem even further.  If too many methods for selecting a topographical path through a device are used, it becomes a very difficult task for tools to be able to model the sequences that have to be performed in order to select or deselect a particular path.  This is even more difficult as you move up in the hierarchy to the board and system levels.

Details

The process for reaffirmation of the group's officers for 2015 was conducted in early March and the results of voting, recorded in the minutes of the March 9th meeting, saw the re appointment of both Ian McIntosh as Chair and Heiko Ehrenberg as Vice-Chair.

Details

An SJTAG Green Paper

By Bradford G. Van Treuren, SJTAG Chair Emeritus

(Full size images may be viewed from the gallery at the foot of this article. A description of SJTAG Green Papers can be found here.)

Abstract

Looking at an entire system to understand the complexity of control and test operations is a daunting task.  Decomposing the problem into smaller pieces does not always provide insights unless one is able to discover commonalities between these levels.  A key insight for SJTAG is the realization that the lowest common denominator for all test and control points in the problem domain is the basic Test Data Register (TDR).  This primitive follows the basic constraint supporting a serial shift protocol implementing a Capture-Shift-Update (CSU) strategy as defined by the IEEE 1149.1 TAP state machine.  Important discoveries is that other control protocols used for system test and configuration (e.g., I2C, SPI, memory mapped) are able to support this same CSU protocol either directly or indirectly using these other interfaces.  How the data is passed through a communication channel down to a TDR is controlled by the AccessLink defining the control aspect of the data and the DataLink that is responsible for transporting the data through that AccessLink.  These concepts for the system and board domains are described in this Green Paper.

  1. Group Officers for 2014
  2. The All New SJTAG Website
  3. Revalidation 2013
  4. User Survey 2009 Results

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Survey 2009

Pages for 2009 Survey results.

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