|A Tale of Two Domains: Preprocessed Tests vs. Interactive Configuration
(A description of SJTAG Green Papers can be found
In this installment, I will be discussing the contrast between the need to support
pre-generated tests, which are able to be replicated for factory testing, versus the need
to support interactive configuration and control of an entity during Design Verification
Test (DVT), Hardware Debugging (HWDB), and Software Debugging (SWDB). Both aspects are
required to support the introduction of new designs. SJTAG needs to be able to support
both these domains. The first usage domain deals with the traditional boundary-scan testing.
A model of a circuit is created that defines the topology of the scan chain. An
algorithm is applied to the model and a set of test vectors are created that can be
applied to circuits matching that topology without needing to regenerate the vectors.
The other domain concerns only a portion of the whole topology: a Test Data Register
(TDR). This application modifies the configuration of one or more data registers
(e.g., TDR) over a period of time to change the behavior of the device the registers
reside in. The flow of the execution may not be the same for each execution of the
application. This is because it is dependent on the state of the device, board, system,
or a combination of some set of effectors monitored during the test operation.
This usage domain is based on supporting the need of structural test techniques, which
may be applied to the same circuit design without requiring the regeneration of the test. The
same technique is then adapted to support programming of devices that adhered to the same
circuit structure and algorithm. This pre-generated testing is only possible if the behavior of
the circuit under test is going to be repeatable no matter how many times the test is
applied. Therefore, the test may be represented as an ordered collection of test vectors
without requiring the persistence of a circuit model to exist during the execution of the
test. The key to making this possible is the vector set is defined to be applied to an
entire circuit topology that does not change its configuration during the test. This
execution model is what is implemented by most boundary-scan tools used today.
Figure 1 Example Board Topology
The traditional interconnect/continuity test is a good example of a test that may be
automatically generated from the CAD data for a board and reapplied to all boards that
match this CAD topology, without needing to be regenerated between each application.
This test uses many different assumptions and testing techniques to handle the
analysis of different types of net architectures. The simplest architecture is a pure
Boundary-Scan architecture where all device pins support IEEE 1149.1 allowing for a full
coverage of testing from one point to the other with full visibility to the connection
end points. Still other architectures may only provide a partial coverage because not
all end points of the circuit are observable or drivable with 1149.1. However, a certain
level of test may still be performed on these circuits to give shorts testing coverage.
The vector patterns are pre-generated and the resulting responses are analyzed as a post
process to determine the state of the circuit under test. So a circuit being tested may
not behave the same as a circuit previously tested, depending on the fault conditions
introduced to the circuit.
To read the rest of this article please follow the link below.
Main article link: http://www.sjtag.org/index.php/news/360-a-tale-of-two-domains-preprocessed-tests-vs-interactive-configuration
From the Chair
SJTAG Officers for 2015
The group's procedure require that the officers are selected or re-appointed on an
annual basis. At this point, the only offices within the group are those of 'chair' and 'vice-chair'.
Technically we have a vacancy for an Editor but that only takes on any relevance once we start to formulate
the draft standard, so it will likely remain vacant until then.
Accordingly, at the meeting held on March 9th, both myself and Heiko Ehrenberg were reaffirmed in the
roles of Chair and Vice-chair respectively.
Website item: http://www.sjtag.org/index.php/news/361-group-officers-for-2015
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