Minutes of Study Group Meeting, 2017-08-14

Meeting called to order: 11:10 AM EDT

1. Roll Call and Introductions

Ian McIntosh (Leonardo MW Ltd.)
Brad Van Treuren (Nokia)
Eric Cormack (DFT Solutions Ltd.)
Bill Eklow (Retired)
Brian Erickson (JTAG Technologies)
Carl Walker (Cisco Systems)
Peter Horwood (Firecron Ltd.)
Adam Ley (ASSET Intertech)
Terry Duepner (National Instruments)
Richard Pistor (Curtiss-Wright)
Naveen Srivastava (Nvidia)
Adam Cron (Synopsys, TTSC) (Auditing)
Heiko Ehrenberg (Goepel Electronics) (joined 11:19)

By email (non-attendees):


2. Role of the group

3. Outline of group policies

4. Schedule of meetings

  • Current timeslot is inherited from the SJTAG Initiative Group. The day/time may be altered if that is the desire of the group.

5. Officers

  • The group does not need TTSC to appoint an Elections Officer as this can be handled internally for study groups.

6. Website awareness

  • Ian briefly showed the existing online assets of the SJTAG Initiative Group. For the time being at least, minutes will be posted on the www.sjtag.org website.

7. Open forum

  • What is the impact on system test? Still seems very "1149-like", how do you deal with that in a system in a rack type of scenario?
  • In the early stages of design (e.g. chip or board) there are good ways to manage DFT. As you move up through the assembly levels there are fewer good, standard tools for that.
  • There is typically no CAD data for how boards are plugged into a backplane.
  • Defining what is a "system": SoCs, one chassis within a rack or several racks connected by wiring harnesses. It can be difficult to determine where the "bottom" is in decomposing a system
  • If a test function of a device or board changes then that has to flow bottom-up through the system. 
  • Are all instruments usable at board level? If not, what makes them unusable? Most DFT functions are added to aid device test on ATE.
  • Challenge can be even knowing features are available. It may not be apparent that a device may have a BIST capability.
  • Board designers may not be considering test so test features may not be made accessible.
  • Don't want to re-invent the wheel, but instead leverage what is in other standards and manage the use of them. Helpful that we have members who are part of other current and past standards development activities.
  • IJTAG offers a good example of how application level test could be achieved if enough 1687 components are provided.
  • The constraints surrounding a device installed in a board or a board installed in a system will be different to those if that item were being tested in isolation during manufacture.
  • External vs Embedded tester: For an embedded test there  may be no direct connection between the top-level test controller - what Ben Bennetts called the Test Manager - and the target: There may be Test Managers/controllers on each board and this would also be true for a distributed test infrastructure/system. It may be very difficult to come up with a single standard to address a distributed test infrastructure/system.
  • Potential for abstraction: Is there something we can do to make the different interfaces look similar?
  • SJTAG looks to be more of a software problem than a hardware one.
  • We'd need to understand how the protocols work from top-to-bottom, although protocols may be more about "behaviour".

8. AOB

  • Poster for ITC: Ian hopes to draft up an outline description over the next few days for a SJTAG poster for ITC. Heiko will be able to present the poster.

9. Topic for next meeting

  • 1687.1 perspective on SJTAG
    • Jeff Rearick in 1687.1 had a slide that attempts to show where the handover from 1687.1 to SJTAG might occur. Brad will attempt to obtain that slide to discuss and perhaps invite Jeff to our meeting.

10. Schedule next meeting

  • August 21.

11. Adjourn

  • Eric moved to adjourn, seconded by Peter.
  • Meeting adjourned at 11:59 AM EDT

Respectfully submitted,
Ian McIntosh