Minutes of P2654 Working Group Meeting No.119, 2021-08-09

 Meeting called to order:  11:09AM EDT

The slide references relate to the pack used during this meeting, located here: 

The cumulative reference pack is located here: http://files.sjtag.org/P2654WG/P2654_Reference_Pack.pptx (updated Dec 31, 2020)

iMeetCentral site: https://ieee-sa.imeetcentral.com/sjtag-sg/ 

1. Roll Call

Terry Duepner (National Instruments)
Brian Erickson (JTAG Technologies) (acting chair)
Louis Ungar (A.T.E. Solutions)
Richard Pistor (Curtiss-Wright)
Jon Stewart (Dell)
Heiko Ehrenberg (GOEPEL Electronics)
Carl Walker (Cisco)
Brad Van Treuren (VT Enterprises Consulting Services)

Tom Thompson (for IEEE)


Ian McIntosh (Leonardo) (chair)
Bill Huynh (Marvell Inc.)
Joel Irby (AMD)
Peter Horwood (Digital Development Consultants Ltd)

2. Agenda

  • Brad moved to accept the agenda, seconded by Terry, no objections.

3. IEEE Patent Slides

  • {Slides 5-10}
  • Patent and Copyright slides reviewed without comment.

4. Review and Approve Previous Minutes

  • {Slide 11}
  • Meeting #118, August 02 (draft circulated August 02)
    • No corrections noted.
    • Terry moved to approve, John seconded, no objections or abstentions → minutes approved.

5. Review Open Action Items

6. Inter-group Collaboration

  • {Slide 13}
  • Clause 7 of P1581 has been identified as needing considerable attention.

7. Discussion Topics

7 a) Delineation between P2654 and P1687.1

  • {Slide 14}
  • Brad talked through his slide pack presented previously to P1687.1 and extended for this meeting: https://github.com/bradfordvt/P2654Model2/blob/main/docs/MJBUnification20210720.pptx
  • Brad presented an overview of C4Model description purpose using the device context diagram. He explained how each box represents a system and tat each box may be further decomposed into sub-systems or containers. The blue colour denotes internal processes or systems. Grey colour indicates an external process or system that the system is dependent on or is a dependent of. Details of notation may be found at com.
  • Brad Reviewed Test Topologies for device and board level contexts. Terry noted view of topologies might need title notation on each page. The figures do have captions that were not visible at the zoom level displayed. That seemed to be sufficient,
  • Figure 1: Device Context is composed of the Device EDA Tooling, the Device Automated Test Equipment, and the Device Under Test systems. The actors involved in the process are: IP Providers, Customers, Architect, Designer, Test Engineer, and Test Operator.  The arrows indicate relationships between the systems and actors.  Brad requested feedback if there were systems or actors missing. Nothing noted.
  • Figures 2 – 5 are similar to Figure 1 but show the context for the board level testing. The difference in each figure is the test equipment used in the process.  Figure 5 represents the embedded test context.
  • Figure 6 represents the System context.
  • Figures 7 – 8 represent the expanded or decomposed view of the Device EDA and Device ATE system contexts respectively.
  • Figure 9 depicts the expanded view of the Board EDA Tooling system. It was noted that each of these sub-systems could be further decomposed.
  • Figure 10 depicts “Board ATPG Tooling” context.  The majority of the meeting time was spent on discussing this figure.
  • Does external tester to P2654 board test model need to be included?  Possibly, but we need to identify the relationship to describe it.
  • ATPG is noted as “static”.  Do we need dynamic TPG as well? Or should this box be just TPG and further decomposed into ATPG and TPG?  The group was leaning this way.
  • Should edits to be made to make tests reusable instead of stating they are static?
  • Discussed whether test granularity should be structural, functional, BIST?  Balance of testing, if it is built right how much test do you need to do? Boundary-scan may be part of the top-level BIST as SVF or STAPL.  How does Multi-Drop BS fit? It is targeting a board, but driven by an external tester.  Brad described his plug-n-play test from his 2005 ITC paper as a tester not needing to know details about the UUT, but that it could play the tests downloaded from the UUT itself to apply to the UUT.  So the tests were still in the context of the UUT.
  • What does Functional really mean?  BIST, Diag, etc.  Where does BIST fall in, is it ATPG?  Does BIST at boot up checkout that same as BIST in respect to this test method?  Is BIST, functionally exercising at speed?  Suggest board level BIST, include structural.  BIST may be part of ATPG, but may not fall completely under ATPG.
  • Higher in hierarchy, less ATPG.  Brad, noted that higher Hierarchy, requires more orchestrating of the test suite.  Louis agreed with BIST, vendors can add as feature, very effective, encouraging in P2654 standard is a benefit
  • MBIST is internal to device.  POST is doing system-level BIST, automated higher level test similar to functional.   Somewhat the same as running functional.  Where does Ext Mem BIST fit into model?  How do we describe model for use-case perspective?
  • Do we need to delineate between BIST families.  Assembly of BIST tests, linking between tests?  Xilinx used to provide internal diagnostic configurations for device level self-test.  Could be accessed from up in hierarchy.
  • Need to have way to describe CPLD controls in lower level to provide test access.  Low level BIST access. What is it and where is coverage.  Brad:  new layout for a slide? ATPG vs manual/scripted generated
  • We further need to know how to discriminate between Functional (at-speed and non-at-speed differences), Structural Test, and BIST (pure hardware-based vs. software-driven differences).
  • Summary: We spent most of the time on Figure 10 in Brad’s C4Model docx file talking about the decomposition of the Board Test Generation tools.  The decomposition shown is wrong. There should be two boxes at a minimum: ATPG and Non-ATPG/Manual/Scripted/Crafted.  The terminology for the second one is not clear right now.  The remaining boxes shown in Figure 10 should be in the decomposition of either or both of the 2 new boxes.

8. Any Other Business

  • {Slide 15}
  • None.

9. Glossary: 

  • better define structural test boundary to functional test

10. Takeaways:

  • Encourage BIST in standard
  • External tester to board test model, does this fit into ATPG/ Static test?
  • Do we need to delineate between BIST families 

11. Schedule next meeting

  • August 16, 2021
    • Jon will be out

12. Topic for next meeting

13. Reminders

14. List New Action Items

15. Adjourn

  • Brad moved to adjourn, seconded by Terry.
  • Meeting adjourned at 12:11 PM EDT

Respectfully submitted,
Brian Erickson & Brad Van Treuren