SJTAG.org - The website for the System JTAG Initiative Group
Supporting eXternal and Embedded Boundary Scan Test
(XBST and EBST)
At the IEEE European Board Test Workshop held in Tallinn, Estonia, May 2005, a group of 14 board test professionals met to discuss a common set of problems associated with the extended test and configuration use of 1149.1 boundary-scan infrastructure within complex multi-board systems. As a result of this discussion, it was decided to create a system-level JTAG initiative, called System JTAG (SJTAG). It also was decided to create a white paper to more clearly define the nature of these problems and hence their possible solutions.
The goal for SJTAG is: For all variants of XBST and EBST, to define the data contents and formats communicated between external Test Manager platforms and internal Embedded Test Controllers,
between ETCs and the UUTs they serve in an open-standard, vendor-independent and non-proprietary way.
This standard defines methods to allow, in conjunction with existing methods, for the coordination and control of device, board, and sub-system test interfaces to extend access to the system level. The standard does not replace or provide an alternative to existing test interface standards, but aims instead to leverage them by defining a description to better manage how they are used in the system.
The purpose of this standard is to provide a means to seamlessly integrate component access topologies (that follow a Capture, Shift, Update cycle), interface constraints, and other dependencies at the board and system level by using a uniform description that focuses on topology and behavior (as opposed to physical structure). By modeling this topology at the board and system level, a set of familiar and yet interchangeable interfaces may be used by higher level tools to coordinate these access topologies and provide a means of routing data sets to particular destination registers in the correct time order.
A standardized method is needed to coordinate component access topologies, interface constraints, and other dependencies at the board and system level in order to be able to effectively leverage the existing and future component level standards. Thus, a new supervisory standard is required to define the coordination and dependencies of instruments as well as configuration, management, and application of vector based testing at the board and system levels. For example, IEEE 1687 and IEEE 1149.1-2013 provide methods for describing each of the instrument interfaces on a per component basis, but do not provide the contextual prerequisites for the dependence on each instrument configuration and/or aggregation of multiple instruments for the overall board and/or system maintenance operations. Further, many components only support non-JTAG interfaces (e.g., I2C or SPI) to their instrumentation registers. This standard will provide a means to utilize the pin level access provided by other standards.