- The website for the System JTAG Working Group

Supporting eXternal and Embedded Boundary Scan Test


At the IEEE European Board Test Workshop held in Tallinn, Estonia, May 2005, a group of 14 board test professionals met to discuss a common set of problems associated with the extended test and configuration use of 1149.1 boundary-scan infrastructure within complex multi-board systems. As a result of this discussion, it was decided to create a system-level JTAG initiative, called System JTAG (SJTAG). It also was decided to create a white paper to more clearly define the nature of these problems and hence their possible solutions.


The goal for SJTAG is: For all variants of XBST and EBST, to define the data contents and formats communicated between external Test Manager platforms and internal Embedded Test Controllers,
between ETCs and the UUTs they serve in an open-standard, vendor-independent and non-proprietary way.


This standard will develop a methodology for access to test, debug, instrument, configuration and/or programming, and emulation features (but not the features themselves) of devices via the IEEE 1149.1 Test Access Port (TAP) for the board and system (multiple board) domains.

The elements for this methodology include a description language(s) describing the structure of how various standards (e.g., 1149.4, 1149.6, 1532, 1687, 1581) and other access mechanisms leverage the IEEE 1149.1 defined TAP interface in the system; a description of data representation formats for test vectors, diagnostic analysis, and data logging; and software application programming interfaces (APIs) defining command primitives facilitating communications between functional command, control, and data modules of an SJTAG Test Manager application.


The purpose of the SJTAG standard is to provide an extension of the IEEE 1149.1 standard specifically aimed at enabling the configuration, control, management, and representation of the communications required at the hierarchical system and board levels to perform operations on the IEEE 1149.1 Test Access Port (TAP) of one or more devices or device cores, in a uniform and transportable way across all system modules.